In the development of semiconductor devices, there is a constant and continuing effort to produce devices having improved performance characteristics such as increased operating frequencies (i.e., speeds), improved signal-to-noise ratios and decreased power requirements compared to predecessor devices, but which can be produced less expensively than predecessor devices. Higher device (component) densities, higher frequencies and data rate capabilities, reduced power requirements and multifunction capabilities on a single chip are being accomplished by the developing large-scale integration (LSI), very-large-scale integration (VLSI) and very-high-speed integrated circuit (VHSIC) technologies.
In the case of devices, increased performance characteristics can be obtained, for example, by decreasing parasitic capacitances, decreasing ohmic losses and decreasing transit times. Those improved performance characteristics can be accomplished, for example, by decreasing the width of source, gate and drain contact metallizations and the spacing between the contacts; increasing the conductivity of the metallizations; more sharply defining the doped areas; and/or by fabricating ohmic contacts having lower resistances.
Presently, interconnects and source, gate and drain contact metallizations of most semiconductor devices and chips are primarily made by conventional photolithographic, chemical etching and sputtering or ion implantation techniques. Photolithographic techniques are technically and economically capable of commercially producing metallizations, contact structures, and inter-contact spacings on the order of about one micron in width. In order to achieve sub-micron widths and thereby effect such desirable improvements as decreased size and increased operating frequencies, resort must generally be made to pioneering electron beam and X-ray lithographic techniques along with fine-line etching techniques such as plasma, reactive-ion, or ion-bombardment etching. At the present time, these pioneering techniques are slower and more expensive, especially in terms of capital equipment costs, than the more conventional lithographic techniques and do not necessarily eliminate such time consuming and troublesome steps as mask alignment steps.
Thus, there is a need for semiconductor devices and chips having near-micron and sub-micron sized component parts and features, e.g., metallizations, contact structures, and inter-contact spacings, and for methods by which those near-micron and sub-micron sized features can be produced reproducibly and inexpensively.